RegViz: Visualize GTCSR Bitfield

Renesas Electronics /R7FA6M1AD /GPT328 /GTCSR

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Interpret as GTCSR

CSELCE=0, CSELCG=0, CSELCF=0, CSCBFAL=0, CSELCD=0, CSCBRAL=0, CSGTRGDF=0, CSGTRGAF=0, CSELCA=0, CSELCB=0, CSGTRGBR=0, CSELCH=0, CSCARBL=0, CSCBRAH=0, CSGTRGAR=0, CSCAFBL=0, CSCBFAH=0, CSELCC=0, CSCARBH=0, CCLR=0, CSGTRGCF=0, CSCAFBH=0, CSGTRGCR=0, CSGTRGBF=0, CSGTRGDR=0

Description

General PWM Timer Clear Source Select Register

Fields

CSGTRGAR	GTETRGA Pin Rising Input Source Counter Clear Enable 0 (0): Disable counter clear on the rising edge of GTETRGA input 1 (1): Enable counter clear on the rising edge of GTETRGA input
CSGTRGAF	GTETRGA Pin Falling Input Source Counter Clear Enable 0 (0): Disable counter clear on the falling edge of GTETRGA input 1 (1): Enable counter clear on the falling edge of GTETRGA input
CSGTRGBR	GTETRGB Pin Rising Input Source Counter Clear Enable 0 (0): Disable counter clear on the rising edge of GTETRGB input 1 (1): Enable counter clear on the rising edge of GTETRGB input
CSGTRGBF	GTETRGB Pin Falling Input Source Counter Clear Enable 0 (0): Disable counter clear on the falling edge of GTETRGB input 1 (1): Enable counter clear on the falling edge of GTETRGB input
CSGTRGCR	GTETRGC Pin Rising Input Source Counter Clear Enable 0 (0): Disable counter clear on the rising edge of GTETRGC input 1 (1): Enable counter clear on the rising edge of GTETRGC input
CSGTRGCF	GTETRGC Pin Falling Input Source Counter Clear Enable 0 (0): Disable counter clear on the falling edge of GTETRGC input 1 (1): Enable counter clear on the falling edge of GTETRGC input
CSGTRGDR	GTETRGD Pin Rising Input Source Counter Clear Enable 0 (0): Disable counter clear on the rising edge of GTETRGD input 1 (1): Enable counter clear on the rising edge of GTETRGD input
CSGTRGDF	GTETRGD Pin Falling Input Source Counter Clear Enable 0 (0): Disable counter clear on the falling edge of GTETRGD input 1 (1): Enable counter clear on the falling edge of GTETRGD input
CSCARBL	GTIOCA Pin Rising Input during GTIOCB Value Low Source Counter Clear Enable 0 (0): Disable counter clear on the rising edge of GTIOCA input when GTIOCB input is 0 1 (1): Enable counter clear on the rising edge of GTIOCA input when GTIOCB input is 0
CSCARBH	GTIOCA Pin Rising Input during GTIOCB Value High Source Counter Clear Enable 0 (0): Disable counter clear on the rising edge of GTIOCA input when GTIOCB input is 1 1 (1): Enable counter clear on the rising edge of GTIOCA input when GTIOCB input is 1
CSCAFBL	GTIOCA Pin Falling Input during GTIOCB Value Low Source Counter Clear Enable 0 (0): Disable counter clear on the falling edge of GTIOCA input when GTIOCB input is 0 1 (1): Enable counter clear on the falling edge of GTIOCA input when GTIOCB input is 0
CSCAFBH	GTIOCA Pin Falling Input during GTIOCB Value High Source Counter Clear Enable 0 (0): Disable counter clear on the falling edge of GTIOCA input when GTIOCB input is 1 1 (1): Enable counter clear on the falling edge of GTIOCA input when GTIOCB input is 1
CSCBRAL	GTIOCB Pin Rising Input during GTIOCA Value Low Source Counter Clear Enable 0 (0): Disable counter clear on the rising edge of GTIOCB input when GTIOCA input is 0 1 (1): Enable counter clear on the rising edge of GTIOCB input when GTIOCA input is 0
CSCBRAH	GTIOCB Pin Rising Input during GTIOCA Value High Source Counter Clear Enable 0 (0): Disable counter clear on the rising edge of GTIOCB input when GTIOCA input is 1 1 (1): Enable counter clear on the rising edge of GTIOCB input when GTIOCA input is 1
CSCBFAL	GTIOCB Pin Falling Input during GTIOCA Value Low Source Counter Clear Enable 0 (0): Disable counter clear on the falling edge of GTIOCB input when GTIOCA input is 0 1 (1): Enable counter clear on the falling edge of GTIOCB input when GTIOCA input is 0
CSCBFAH	GTIOCB Pin Falling Input during GTIOCA Value High Source Counter Clear Enable 0 (0): Disable counter clear on the falling edge of GTIOCB input when GTIOCA input is 1 1 (1): Enable counter clear on the falling edge of GTIOCB input when GTIOCA input is 1
CSELCA	ELC_GPTA Event Source Counter Clear Enable 0 (0): Disable counter clear on ELC_GPTA input 1 (1): Enable counter clear on ELC_GPTA input
CSELCB	ELC_GPTB Event Source Counter Clear Enable 0 (0): Disable counter clear on ELC_GPTB input 1 (1): Enable counter clear on ELC_GPTB input
CSELCC	ELC_GPTC Event Source Counter Clear Enable 0 (0): Disable counter clear on ELC_GPTC input 1 (1): Enable counter clear on ELC_GPTC input
CSELCD	ELC_GPTD Event Source Counter Clear Enable 0 (0): Disable counter clear on ELC_GPTD input 1 (1): Enable counter clear on ELC_GPTD input
CSELCE	ELC_GPTE Event Source Counter Clear Enable 0 (0): Disable counter clear on ELC_GPTE input 1 (1): Enable counter clear on ELC_GPTE input
CSELCF	ELC_GPTF Event Source Counter Clear Enable 0 (0): Disable counter clear on ELC_GPTF input 1 (1): Enable counter clear on ELC_GPTF input
CSELCG	ELC_GPTG Event Source Counter Clear Enable 0 (0): Disable counter clear on ELC_GPTG input 1 (1): Enable counter clear on ELC_GPTG input
CSELCH	ELC_GPTH Event Source Counter Clear Enable 0 (0): Disable counter clear on ELC_GPTH input 1 (1): Enable counter clear on ELC_GPTH input
Reserved	These bits are read as 0000000. The write value should be 0000000.
CCLR	Software Source Counter Clear Enable 0 (0): Disable counter clear by the GTCLR register 1 (1): Enable counter clear by the GTCLR register

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